////`default_nettype none   
//synthesis translate_off 
`include "../../timescale.v"  
//synthesis translate_on
`include "../../DSP_define.v"
module tb_IF_stall;
reg    sys_clk;
reg    DP_stall;
reg    I_FP_invalid;
reg    D_RAM_invalid;
wire   stall;

initial 
    sys_clk=1'b1;
    
always #10 sys_clk = ~sys_clk; 

initial 
begin
  #0  DP_stall=1'b0;
      I_FP_invalid=1'b0;
      D_RAM_invalid=1'b0; 
  #20 DP_stall=1'b1;
      I_FP_invalid=1'b0;
      D_RAM_invalid=1'b0;
  #20 DP_stall=1'b1;
      I_FP_invalid=1'b1;
      D_RAM_invalid=1'b1;      
  #100 $stop;
end 
    
IF_stall   IF_stall_Compt1(
                          .DP_stall(DP_stall),
                          .I_FP_invalid(I_FP_invalid),
                          .D_RAM_invalid(D_RAM_invalid),
                          .IF_stall(stall)
                          );                          
                                                    
endmodule

//
//integer i,err_count;
//
////generate clock signal
//initial 
//  begin
//    //$timeformat(-9, 1, " ns", 5);
//    clk=1;
//    err_count=0;
//  end  
//always #10 clk = ~clk; 
//
////assignment&simulate
//initial
//  begin
//    $display("*************************************************************");
//    $display("*************Begin to test IF_stall module!******************");
//    $display("*************************************************************");
//    begin
//      for(i=0; i<=7;i=i+1)
//        @(posedge clk) //it can delay DP_stall,I_FP_valid,D_RAM_valid for 20,because before this time the clock din't generated!
//        begin 
//           {DP_stall,I_FP_invalid,D_RAM_invalid}=i;               
//           #11 if(({DP_stall,I_FP_invalid,D_RAM_invalid}>=1)&&(stall==1'b0))
//                 begin
//                   $display("Error at time %t: DP_stall=%b,I_FP_valid=%b,D_RAM_valid=%b;
//                                    \nstall=%b Expected stall=1",
//                                    $time, DP_stall,I_FP_valid,D_RAM_valid, stall);
//                   err_count = err_count + 1'b1;
//                 end
//           #4;  //i was evaluated after #15 delay!
//        end
//    end
//    
//    $display("*******************************************");
//    $display("***Complete IF_stall Tests with %0d Errors!***", err_count);
//    $display("*******************************************");
//
//    begin
//      for(i=0; i<=7;i=i+1)
//        @(posedge clk)//it can delay DP_stall,I_FP_valid,D_RAM_valid for 20,because before this time the clock din't generated!
//        begin 
//           {DP_stall,I_FP_invalid,D_RAM_invalid}=~i;               
//           #11 if(({DP_stall,I_FP_invalid,D_RAM_invalid}>=1)&&(stall==1'b0))
//                 begin
//                   $display("Error at time %t: DP_stall=%b,I_FP_invalid=%b,D_RAM_invalid=%b;
//                                    \n stall=%b Expected stall=1",
//                                    $time, DP_stall,I_FP_invalid,D_RAM_invalid, stall);
//                   err_count = err_count + 1'b1;
//                 end
//           #4;  //i was evaluated after #15 delay!
//        end
//    end
//    
//    $display("*******************************************");
//    $display("***Complete IF_stall Tests with %0d Errors!***", err_count);
//    $display("*******************************************");
//    $finish;
//  end  

